The present invention relates to an arithmetic unit, an address generator and a program controller which are used in a digital signal processor (hereinafter simply referred to as DSP).
In recent years, the DSP has been used frequently in, for example, a digital portable telephone. In the DSP to be built in an apparatus as above, the fixed-point arithmetic is often carried out to suppress consumptive power and costs and in that case, the number of significant digits or bits of data to be used for calculation is sometimes changed in conformity with the required accuracy of calculation for the signal processing.
In a prior art, when the number of significant bits of data used for calculation is smaller than the bit width of an arithmetic circuit, efforts are made to increase the speed of the processing for masking or shifting input/output data, to match it with the bit width of the arithmetic circuit. For example, JP-A-2-293928 discloses a configuration which uses an arithmetic and logic mechanism of variable operational word length.
The prior art will be described hereunder with reference to FIG. 7 showing, in block form, a conventional arithmetic unit of a microcomputer. In the prior art, an operational word length setting circuit 101 sets significant bits of the arithmetic circuit, data correcting circuits 103 and 104 respond to a control signal from the setting circuit to generate calculation data supplied to the arithmetic circuit, an arithmetic and logic circuit 100 of variable operational word length responds to the control signal from the setting circuit and data from the data correcting circuits to perform calculation, a bit accuracy setting circuit 102 controls the significant bits of an output result of the arithmetic circuit, and a bit accuracy correcting circuit 106 responds to a control signal from the setting circuit to correct the significant bits. In the arithmetic unit constructed as above, calculation input data and data of calculation results are masked or shifted to ensure that load on software for matching the arithmetic significant digit can be reduced to improve the processing speed of the whole system.
In the prior art arithmetic unit, however, data having the same bit width as that owned by the arithmetic circuit and being larger than the significant digits of the data is supplied from the data correcting circuit to the arithmetic circuit and besides, the transfer of a carry is not controlled in the arithmetic circuit, raising a problem that even a portion of the arithmetic circuit which is unnecessary for calculation of the significant bits is operated to increase power consumption.
In another example where the DSP is so used as to be built in an apparatus, the number of words installed in a data memory and an instruction memory is often changed to match the number of words used in an application program of the apparatus in which the DSP is built. For example, even when a data address register of a DSP is of 16 bits and accordingly, an address space of 2.sup.16 i.e., 65536 words can be designated to a data memory, a semiconductor chip of the DSP is often installed with a data memory for only 256 words if the capacity of the data memory actually used by programs to be executed is known as being 256 words. Through this, the area of the semiconductor chip can be decreased to reduce the cost. In this case, however, the 256-word address space of the data memory can be designated using 8 bits at the most, raising a problem that the address generator included in the DSP and having the address register of 16-bit width is superfluously operated by 8 bits.
The instruction memory also faces a similar problem. If the number of lines of a program to be executed is 256 words, the capacity of an instruction memory installed is sometimes of only 256 words. When the bit width of a program counter of the DSP is 16 bits, there arises a problem that a program controller included in the DSP having the program counter is superfluously operated by 8 bits.